1. Field of the Invention
The present invention relates to circuits used for performing arithmetic operations, and more specifically to a method and apparatus for performing a conditional subtract operation typically used in a division arithmetic operation.
2. Related Art
Conditional subtract instructions are often used to perform division operations. In one known environment, a conditional subtraction instruction is specified in the format (subcu ACC, mem), wherein subcu is a pneumonic specifying that it is a conditional subtraction instruction, ACC specifies an accumulator containing a first operand, and mem specifies a memory location containing a second operand. The instruction is defined to operate according to the following equations:aluout=ACC−(mem<<(M−1)bits)  Equation (1)If (aluout.ge.0)then ACC=(aluout<<1)+1  Equation (2)else ACC=ACC<<1  Equation (3)
wherein aluout represents the output of arithmetic logic unit, ‘<<’ indicates a shift operation by a number of bits specified on the right hand side, ‘.ge’ represents the greater-than-or-equal-to logical operation, M represents the number of bits in the dividend, and mem represents a memory storing the divisor.
Thus, the operand at the memory location is left-shifted by (M−1) bits and the shifted value is subtracted from the value in the accumulator. If the result is greater than or equal to zero, accumulator is set to a value resulting from left shifting aluout by 1 position and adding a 1. Otherwise, the value in the accumulator is left-shifted by 1 position.
When a division operation is sought to be performed, the accumulator is initially loaded with the dividend and the divisor is provided at the memory location mem. The conditional instruction (Equations 1-3) is repeated several times to generate the remainder and the quotient in the accumulator. The instruction is repeated a number of times equal to the number of bits in the dividend. At the end of the iterations, the accumulator contains the quotient and the remainder.
For example, assuming a four-bit dividend of 7 (0111 in binary), a four-bit divisor of 5 (0101), and an eight bit (2×N, wherein N represents the number of bits of dividend) accumulator, the accumulator is initialized with 0000 0111 (7), and the memory (at location mem) is set to 0000 0101. The conditional subtraction instruction is then performed 4 times.
In the first iteration, 00101000 (operand at mem shifted by 3 positions, wherein) is subtracted from 0000 0111 (7). As a negative result is obtained, accumulator is left shifted by one position. A negative result would be obtained for two additional iterations. In the fourth iteration, 00101000 is subtracted from 00111000 (dividend shifted by three bit positions), and equation causing a value of 0010 0001 to be stored in the accumulator by virtue of Equation (3).
The most significant four bits represent the remainder and the remaining four bits represent the quotient. While the example illustrates the division of N bit dividend with a N bit divisor (“N/N division”) using a 2N bit-width accumulator and ALU, the same approach can be used to implement divisions of longer length divisions as is well known in the relevant arts. For further details on implementing division operations using conditional subtraction instructions, the reader is referred to a document entitled, “TMS320F/C24×DSP Controllers Reference Guide: CPU and Instruction Set”, Literature number: SPRU160C, dated: June 1999, available from Texas Instruments, Inc. (the assignee of the subject application), which is incorporated in its entirety herewith.
From the above, it may be appreciated that the conditional subtraction instruction is used many times during a division operation. Thus, to complete a division operation quickly, it is generally necessary to perform conditional subtraction instruction also quickly. Quickness (speed) may be of particular concern in areas such as digital signal processors which may be employed in real time applications. Accordingly, there is a general need to improve the speed with which a conditional subtraction instruction is executed.